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| Logical Constraints
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Logical constraints are required to specify signal relationships that make the overlaying protocols work. For example, in a source synchronous bus, there is a relationship between the clock and data signals. Pin assignment process should consider higher_level protocols to ensure that the correct signal relationships are maintained. This is required because FPGA I/Os have special function pins and pin groups to enable higher -level protocols to work. For example:.
- Source synchronous bus signals in Xilinx Virtex-5 architecture should all be within the same clock region, as defined by the architecture.
- The clock signals of a source synchronous bus in Xilinx Virtex-5 architecture should be connected to special pins in the clock region.
- A group of DQ/DQS pins have to be assigned to a set of pre-defined pins in Altera Stratix II/III architectures.
7Circuits provides ways for the user to specify the logical constraints. Once the logical constraints are defined, 7Circuits will ensure they are followed while synthesizing I/Os.
Figure 1 shows an example of how logical relationships are shown. Figure 2 shows how certain grouped signals are all allocated to the same bank to follow the required logical constraint.
Figure 1. Adding constraints to specify logical relationships. |
Figure 2. DQ and DQS connected to the same bank - Logical Constraint. |
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Logical Constraints
