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| Executive Team |
Nagesh Gupta
CEO
Nagesh started his career designing and verifying PA RISC processors for Hewlett Packard in Cupertino. Later, Nagesh ran Engineering for a wireless networking startup, Redwave Networks. Nagesh founded Taray in 2002 to solve challenges related to FPGAs. At Taray, Nagesh envisioned and created "Memory Interface Generator", which is a currently delivered by Xilinx, through Coregen.
Nagesh has more than 17 years of experience in hands on engineering roles as well as managing small to large groups for product delivery. Nagesh has a Bachelor’s degree in Electrical & Electronics Engineering from B.I.T.S, Pilani, India, and a Master’s in Electrical Engineering from University of Kansas, Lawrence. |
Joe Gianelli
VP Marketing & Business Development
Joe has extensive experience and a proven track record in the electronic design automation industry. Joe's background in EDA includes; Daisy Systems as a test engineer, ECAD as a training instructor and applications engineer, Cadence Design Systems as training instructor, applications engineer, technical marketing engineer, and product manager, Meta Software as technical marketing engineer and account manager, EPIC Design as an Sr. account manager, and Synplicity as a channel marketing director and VP of business development.
Joe is currently responsible for all marketing and business development activity for Taray. |
Sarala Beeneedi
VP FPGA
Sarala has been associated with Taray ever since its inception. She has been instrumental in the success of Taray's products. Sarala has more than 20 years of experience in VLSI, ASIC and board designs. Sarala has worked both in India and in the United States.
Sarala has a Bachelor's degree in Electronics and Communications from Institute of Electronics and Telecommunications, Delhi, and a Master's degree in Advanced Electronics from JNTU, Hyderabad. |
Ravi Vedula
VP EDA
Ravi started his career developing EDA tools and simulation models. Prior to
joining Taray, Ravi managed R&D teams at various levels for tool
development and chip design methodologies specifically in the areas of
timing analysis, circuit simulation/modeling, cell characterization,
and printed circuit board design/layout at Cadence, Motorola and Mentor
Graphics.
Ravi has a Bachelor’s degree in Electronics
& Communication Engineering from Osmania University and a Master’s
in Electrical Engineering from IIT, Delhi. |
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